Malicious modifications to hardware from insiders pose a significant threat today. The complexity of hardware systems and the large number of engineers involved in the designing of them pose a security threat, because it is easy for one malicious individual to alter one tiny piece of a system. Although this behavior is very risky, it can be very profitable for an attacker, because a hardware backdoor provides a foothold into any sensitive or critical information in the system. Such attacks can be especially devastating to security-critical domains, such as military and financial institutions. Hardware, as the root of the computing base, must be trustworthy, but this trust is becoming harder and harder to assume.
A malicious modification or a backdoor can find its way into a design in several ways. The modification could come from a core design component, e.g., a few lines of Hardware Design Language (HDL) core code can be changed to cause malicious functionality. The use of third-party intellectual property (IP) provides another opportunity. Today's hardware designs use an extensive array of third party IP components, such as memory controllers, microcontrollers, display controllers, digital signal processor (DSP) and graphics cores, bus interfaces, network controllers, cryptographic units, and an assortment of building blocks, such as decoders, encoders, content-addressable memory (CAMs) and memory blocks. Often these units are acquired from vendors as HDL implementations and integrated into designs only after passing validation tests without code review for malicious modifications. Even if complete code reviews are possible, they are extremely unlikely to find carefully hidden backdoors, as evidenced by the fact that non-malicious modern designs ship with many bugs today.
An aspect of hardware backdoors that makes them so hard to detect during validation is that they can lie dormant during (random or directed) testing and can be triggered to wake up at a later time. Verification fails because designs are too large to formally verify, and there are exponentially many different ways to express a hardware backdoor.
Hardware backdoor protection is a relatively new area of research that protects against a serious threat. Recently, some attention has been given to protecting hardware designs from hardware backdoors implanted by malicious insiders, but there are currently only two known solutions that have been proposed. A method has been designed for statically analyzing register-transfer level (RTL) code for potential backdoors, tagging suspicious circuits, and then detecting predicted malicious activity at runtime. This hardware/software hybrid solution can work for some backdoors and even as a recovery mechanism. Its admitted weaknesses are that the software component is vulnerable to attack and additionally that the software emulator must itself run on some hardware, which can lead to infinite loops and DOS (denial of service).
There has been work in tangentially related areas of hardware protection, usually leveraging a trusted piece of the design or design process. Significant work has been done (mainly in the fabrication phase) toward detecting active backdoors, analyzing side-channel effects, detecting suspicious path delays and detecting backdoors added at the fabrication level. However, all of this work assumes that the properties of the backdoors are limited and that there is a golden netlist (trusted RTL description). The reason for this common assumption of a trusted front end code base is that code is often written by insiders whereas the manufacturing process is often outsourced. However, increasing design team sizes and increasing use of third party IP on-chip are making this assumption about the front end less realistic.
A fundamental difference between the embodiments described herein and previous work is that since we disable the backdoor at its origination point—the trigger—we provide a much more general solution than previous approaches. Both previous solutions use deterministic methods to protect against a subset of the attack space. Our methods, by contrast, provide probabilistic guarantees against all deterministic, digital backdoor triggers. Unlike other methods, our scheme can prevent DOS attacks.